Embodiments of the present invention relate to a semiconductor device including a buried gate, and more particularly to a semiconductor device having a buried gate, which does not include a PN junction between a source and a body or between a body and a drain.
Generally, a semiconductor is a material that falls in category between a conductor and a nonconductor among materials affected by electrical conductivity. Although a pure semiconductor is similar to a nonconductor, electrical conductivity of the semiconductor increases by impurity implantation or other manipulation. The semiconductor is used to form semiconductor devices through the impurity implantation and/or conductor connection. A representative example of the semiconductor devices is a semiconductor memory device.
A semiconductor memory device includes a plurality of transistors. A transistor has three regions, i.e., a gate, a source, and a drain. Electric charges move between the source and the drain according to a control signal (the magnitude of voltage) input to the gate of the transistor. The charges moves between the source and the drain through a channel region formed under the gate in accordance with properties and operations of the semiconductor device.
Generally, a method for manufacturing a transistor includes forming a gate over a semiconductor substrate and forming a source and a drain by doping impurities into portions of the semiconductor substrate located at both sides of the gate. In this case, a region between the source and the drain and below the gate is used as a channel region of the transistor. If a transistor including a horizontal channel region is used, it is difficult to reduce the overall area of a semiconductor device including a plurality of transistors since the plurality of transistors, each including a horizontal channel region, occupies a substantial area.
In order to solve the above-mentioned problem, a three-dimensional (3D) transistor including a vertical gate, such as a recess gate, a fin gate, or a buried gate, in which all or some parts of the gate are buried by etching a semiconductor substrate, has been proposed.
However, even if a semiconductor device includes 3D transistors, a memory cell still uses an NMOS transistor in which P-type impurities are implanted into a channel region formed below a gate oxide film and high-density N-type impurities are implanted into a source/drain region. Accordingly, multi-stage ion implantation processes are needed for manufacturing the NMOS transistor.
In addition, if a gate is buried in a semiconductor substrate in the same manner as in a buried gate, an overlapping region is generated between the gate and a source/drain region. However, if the gate overlaps with the source/drain region, Gate Induced Drain Leakage (GIDL) characteristics change according to the size of the overlapping region. As a result, retention characteristics capable of maintaining data stored in a capacitor also change. That is, buried gates may be formed to have different heights when a buried-gate material is etched back in a buried gate structure. In this case, overlapping regions of respective cell transistors are irregularly formed so that a large difference may occur in retention characteristics of respective cells, resulting in the occurrence of a serious problem in a semiconductor device composed of gigabit cells.